Joo-Tae Moon* and Moon-Yong Lee

Semiconductor R&D Center, Samsung Electronics Co. Ltd., Korea
jtmoon@samsung.co.kr

Plasma technology in fabrication of sub-quarter micron ULSI devices is being confronted with various challenges. Recent ULSI devices involve very thin gate oxide down to about 50 A and various silicide gates such as TiSix and CoSix for the high performance of the transistors. It also requires self-aligned contact (SAC) holes and very small deep contact holes to implement the complex 3D storage nodes into the capacitor structures and the CMP processes.

The lateral etching of silicides in the chlorinated plasma is so severe that we need to control the profiles by adding a passivation gas such as HBr, N2 or O2, which, however, may result in microloading. Also, the pulse plasma technique of low electron temperature is being developed for the profile control, and it is expected to alleviate the electron shading damage during the gate etching.

The most outstanding issues in SiO2 etching lie in the SAC and small deep contact hole etching. The first of these issues is to maintain the small feature size and good profiles. We need to have high selectivity to SiN in SAC processes as well as to Si because the SiN is used to electrically isolate the gate lines from the contact holes. To meet the etching requirements, we are investigating the dissociation and polymerizaton of various CxFy gases. We are also investigating the effects of the chamber wall materials and temperature with the help of quadrupole mass spectrometry, OES, and in-situ FTIR.